Tim Edwards

08/06/2020, 5:09 PM
@User: The "harness" is what we've been calling the whole chip that will be the carrier for user projects starting with the November shuttle run (it now has a name---Caravel). The chip (tentatively, not finalized but soon to be) has a size of 3.2mm x 5.3mm . About 1/4 to 1/3 of that will contain a small RISC-V processor (a picoRV32, since we've taped out several versions of it) which can be used for access to the user projects. Some portion of the padframe will be used by the processor, and the rest will be in the user space (inside the padframe). We intend to let the users swap out some set of pads in the user space for other compatible pads, although the set of pads to choose from is somewhat limited. The padframe is 200um wide, so the user space will be something like 3.2mm x 2.8mm, or 9mm^2, more if we can manage it (the original intent was 10mm^2 of user space, and we'll hit that number if we can, although the original area was not accounting for the amount taken up by the padframe).
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