<@U016PTY0C2E>: The all-digital PLL as designed c...
# shuttle
t
@User: The all-digital PLL as designed can get to about 200MHz, but it can be made to go faster; it was designed to drive the picoRV32 processor, so it was not designed for maximum speed, but to cover the range of the processor core over process/voltage/temperature. You would have to ask the openlane developers what they got for the maximum clock rate on the striVe picoRV32 core. I think it is around 100MHz or a little higher, nominal.