Tim Edwards

10/13/2020, 2:43 AM
@User: The I/O library is nearing completion and I hope to make a first cut at the padframe layout tomorrow. I won't be able to give you the exact dimensions until we (1) synthesize the management SoC core and figure out how much space it's going to take up, and (2) synthesize the GPIO pad control blocks and the routing to them to see how much they are going to intrude upon the user space (hopefully they just fit under the power buses and don't take up any appreciable space), and (3) do a test layout of the redistribution metal layer to make sure that the width of the chip accommodates the number of bump bonds we want without causing DRC violations on the redistribution metal width and spacing.