I have a question about hardening designs with OpenLane for inclusion into Caravel. Following this guide https://github.com/efabless/caravel/blob/develop/openlane/README.md Suggests two options. If Option 1 is taken, that is to harden the design separately and insert it into user_project_wrapper afterwards. The OpenLane flow spits out a GDS and LEF for the user's hardened design. When the hardened design is inserted into user_project_wrapper, it is "hotswapped" in with that GDS and LEF, by putting such things into the config file:

set ::env(VERILOG_FILES_BLACKBOX) "\
	$script_dir/../../verilog/rtl/user_proj_example.v"

set ::env(EXTRA_LEFS) "\
	$script_dir/../../lef/user_proj_example.lef"

set ::env(EXTRA_GDS_FILES) "\
	$script_dir/../../gds/user_proj_example.gds"

So that's the set-up. My question is the following: does timing data get generated for the user's hardened design, so that it can be imported into the next OpenLane run? Maybe I just haven't gotten that far quite yet.