<!channel>: The efabless prototype chip that we taped out earlier last year to test our understanding of the process, the IP libraries, and the openlane digital flow has returned, been packaged and assembled, and put on the bench. Today it is showing signs of life, signalling to the SPI flash chip. That validates that the GPIO pads are working properly, and the synthesized digital logic is running, and my confidence just took a giant leap upward from yesterday. I'll keep you posted as testing continues.