Hey folks, I have three questions about a macro I'm making with OpenLane (I am not using caravel_user_project, just OpenLane directly, then this macro will be incorporated into a design): 1. I'd like to be pretty sure that there aren't antenna check issues with my macro before Weston integrates it into what he's submitting. Synthesis failed when I tried to use

DIODE_INSERTION_STRATEGY = 1

(spray diodes), but synthesis works fine with

DIODE_INSERTION_STRATEGY = 3

(FastRoute's antenna avoidance). It failed saying

[WARNING DPL-0005] Overlap check failed (14269)

. My main question: If I can't use

DIODE_INSERTION_STRATEGY = 1

, is there some easy way I can just guarantee that every input pin has diodes? Or will they all already have diodes? 2. Secondly, I see these reported in

manufacturability_report.rpt

(again, synthesizing with

DIODE_INSERTION_STRATEGY = 3

):

Antenna Summary:
Source: /openLANE_flow/designs/snproc/runs/run7_rev2_mem512/reports/routing//41-antenna.rpt
Number of pins violated: 960
Number of nets violated: 651

How scared should I be of that? 3. Finally, I'd like to perform some sort of LVS check. I see a

results/lvs/

directory that contains some log files reassuring me that no mismatches were found. Are these checks performed on the final GDS all the way back to the first netlist? If not, do folks have advice on running an LVS, and which is the best netlist to LVS the GDS against? (Done: Weston helped me with this.)