We are using a hierarchical approach for our design and when running our top module through the flow we are encountering the following error on LVS:

4577 Net: i_tile_x3y4/vccd1                     |(no matching net)
4578   tile_clb/vccd1 = 1                       |                                                                                                                                                                                               4579                                            |                                                                                                                                                                                               4580 Net: i_tile_x3y4/vssd1                     |(no matching net)                                                                                                                                                                              4581   tile_clb/vssd1 = 1                       |                                                                                                                                                                                               4582                                            |

tile_clb is an already hardened macro of our design. I found some mentions of setting FP_PDN_MACRO_HOOKS to resolve the issue. Is this the correct approach or is there something else that we need to resolve? Also, if someone can point me to a repository with a successful hierarchical tapeout using Caravel that would be really helpful. Thank you in advance!