I’ve been working on a system for full chip device level LVS and CVC-RV for caravel/caravan designs. (CVC-RV is similar to Calibre PERC, i.e. reliability verification. Not to be confused with OSS CVC which is a verilog simulator.) Hopefully eventually, all the required modifications will be incorporated into the openlane flow, but most likely not before the mpw-5 tapeout deadline. The caravel/caravan framework may not be fixed at the moment, but it is possible to check

user_project_wrapper

and

user_analog_project_wrapper

. I ran LVS and CVC-RV checks on the mpw-2 designs at that level and found fatal errors in 7/40. So here’s the offer. If you have a design for mpw-5 that has passed prechecks, has all verilog blocks as powered gate level verilog in

verilog/gl

and has all analog blocks as spice in

spi/lvs

in your repo, I’ll run device level LVS, CVC-RV, and soft connection checks for wells for you. Financial contributions are appreciated but not necessary (at least for mpw-5). If you’re interested, DM me.