Hi all I m using Innovus to implement our tiny fpga

Question

Hi all I m using Innovus to implement our tiny fpga <https github com FPGA Research Manchester FABulous SKY130> It looks OK for P amp R but a lot of DRC Antenna violations occur Have anyone encountered the following violations after P amp R in Innovus Openlane Any ideas how to fix them Thanks Verify Connectivity UnConnPin Violations 1000 Net VGND FE DBTC3 Tile X3Y3 E2BEG 5 VNB False No Layer pwell Bounds 100 425 561 935 100 595 562 105 gt for all power nets I think Verify Overlap Overlap Violations 1000 Blockage of Cell FILLER 91589 amp Blockage of Cell Tile X2Y4 LUT4AB Inst LUT4AB switch matrix 4240 False No Layer M1 Bounds 807 300 866 575 808 220 866 745 Regular Wire of Net Tile X1Y1 LUT4AB Inst LUT4AB switch matrix 0321 Actual 0 0000 Required 0 0000 Type Antenna Area Ratio False No Layer M4 Bounds 574 730 94 870 575 730 95 870 Regular Wire of Net Tile X3Y2 W2BEGb 1 Actual 0 0000 Required 0 0000 Type Antenna Area Ratio False No Layer M5 Bounds 703 530 299 210 704 530 300 210 Regular Wire of Net Tile X0Y2 B O top Actual 0 0000 Required 0 0000 Type Antenna Area Ratio False No Layer M6 Bounds 455 590 146 890 456 590 147 890 Regular Wire of Net Tile X1Y2 LUT4AB Inst LUT4AB switch matrix 0757 Actual 1 4200 Required 1 6000 Type Minimum Width False No Layer M6 Bounds 802 360 111 800 826 640 113 220 From the layout view it looks fine e g overlap between VGND and VNB pins pwell or the width of M6 wires are 1 6 but not sure what cause those violations