For those joining: GHDL + Yosys is at the moment pretty close to production ready. We have been sending the maintainer bug reports. At the moment it can synthesize complex designs (J-Core, Miniwatt) and the yosys plugin works quite well. One can produce bitstreams that work for e.g. ice40. All constructs we use work properly, but name mangling of some complex types into simple yosys/verilog compatible names is a bit frustrating if you're trying to read the resulting netlists.