Whoever wants. But I have to go to bed now. See you tomorrow!

see you, let me know tomorrow and we could set something up

I'm told Samsung is trying to do a 4 nanometer fab in my home city (https://wccftech.com/samsung-1-billion-texas-chip-foundry/) but wikipedia[citation needed] still has them at 11nm.

Current reality distortion field in ASIC development...

@User cool!

Oh, did I ever link on here?

Jeff linked it over on #j-core

The talk after ours in the playlist is about the VHDL toolchain we posted that old build script for.

(The fully open source bitstream generator for lattice one.)

Woo, Jeff says the latest gui build of the GHDL+Yosys bitstream toolchain fits the J1 system we put on github into 79% of an ICE40 up5k and meets faster timing.

(That's not even the current one, we've been doing some optimizing but it's not ready to use yet...)

20% free lets us cram an extra subsystem in there...

There's also a work in progress VHDL netlist writer. https://github.com/rlee287/ghdl-yosys-plugin

I wonder what synth_formal is? https://github.com/ghdl/docker/blob/master/synth_formal.dockerfile

@User has left the channel

So I joined awhile back and now everything I want is behind a 'unlock messages' nonesense

would anyone else be willing to switch to a mattermost server? I could set it up and host it for free

Since September/October most of the channels on Skywater-pdk Slack workspace are bridged to Matrix:https://matrix.to/#/+skywater-pdk:matrix.org There is no paywall on Matrix.

Hello all, is there anyway to simulate VHDL and Verilog designs together. I have my designs in Verilog but test gen in VHDL. Posted in #digital-design

@User yes you can, but not with open source tools. If you want to do it for free the xilinx vivado simulator is probably your best bet

Maybe the Intel modelsim version will too, but I've never used that

@User thanks for your answer. I have seen a method using ghdl-yosys plugin where the input is vhdl and output is verilog. Any idea or comment on that.

Never tried it, maybe it works. It's really up to you if you want to try workarounds (and potentially improve them) or proceed with a commercial choice or just rewrite the VHDL part to verilog or vice versa - sometimes that like last option is quicker than days bashing your head against tools

Experience with ghdl-yosys is a question for https://gitter.im/ghdl1/Lobby I think

Are there any instructions on using GHDL with OpenLANE?

@Matt Venn has left the channel

I noticed that this Rust-based VHDL language server has been getting quite a few updates recently and the author (Olof Kraigher) describes it like this: It is now in a really good state and is ready to be the daily driver for someone working on VHDL. It is completely free and open source, enjoy! https://github.com/VHDL-LS/rust_hdl The easiest way to try is the VSCode extension by Henrik Bohlin: https://marketplace.visualstudio.com/items?itemName=hbohlin.vhdl-ls

@Mohammed Fayiz Ferosh has left the channel