@User i got this far: Yosys 0.9+2406 (git sha1 000fd081, clang 10.0.0 -fPIC -Os) yosys> ghdl register_file 1. Executing GHDL. register_file_sync.vhd10910note found RAM "bank_a", width: 32 bits, depth: 32 register_file_sync.vhd10918note found RAM "bank_b", width: 32 bits, depth: 32 Importing module register_file.