https://open-source-silicon.dev logo
Title
a

AndrewSftD

07/08/2020, 11:55 AM
Yosys 0.9+2406 (git sha1 000fd081, clang 10.0.0 -fPIC -Os) yosys> ghdl cpu 1. Executing GHDL. decode.vhd:71:5:note: found ROM "n340", width: 13 bits, depth: 21 decode_core.vhd:167:61⚠️ comparing non-numeric vector is unexpected register_file_sync.vhd:109:10:note: found RAM "bank_a", width: 32 bits, depth: 21 register_file_sync.vhd:109:18:note: found RAM "bank_b", width: 32 bits, depth: 21 Importing module cpu. Importing module decode. Importing module mult. Importing module datapath. Importing module decode_core_0_7b7173a846209ae0b859b138e5be90c988fc1dd9. Importing module decode_table. Importing module register_file_5_21_32.