But again J2 is 2x SMP with L1 cache and DRAM controller an open-source-silicon.dev #vhdl

(But again, J2 is 2x SMP with L1 cache and DRAM co...

Rob Landley

07/08/2020, 2:33 PM

(But again, J2 is 2x SMP with L1 cache and DRAM controller and so on...)