That board has the up5k FPGA in QFN48, yes. That ...
# vhdl
j
That board has the up5k FPGA in QFN48, yes. That repo will build by default for the GPIO on that board, but the clock is coming from IIRC pin 20, which isn't connected on upduino 2.0. I'll see about connecting it to the internal HF oscillator... there was a bug in the yosys mapping for that a few months ago I saw the fix go by but I never revisited it.