10/08/2020, 6:48 PM
I'm running:
(layout) 20 % lvs divider_cml_orig.spice divider_cml.spice
Comparison output logged to file comp.out
Logging to file "comp.out" enabled
Contents of circuit 1:  Circuit: 'divider_cml_orig.spice'
Circuit divider_cml_orig.spice contains 16 device instances.
  Class: sky130_fd_pr__res_xhigh_po_2p85 instances:   4
  Class: sky130_fd_pr__rf_nfet_01v8_lvt_cM02W1p65L0p15 instances:  12
Circuit contains 13 nets.
Contents of circuit 2:  Circuit: 'divider_cml.spice'
Circuit divider_cml.spice contains 0 device instances.
Circuit contains 0 nets.

Circuit divider_cml.spice contains no devices.
Result: The top level cell failed pin matching.

Logging to file "comp.out" disabled
LVS Done.