@User I'm trying to do LVS with an "analogue-on-top" approach, ie. xschem and klayout driven top level but using openlane generated blocks in the heirarchy for some functionality. One of the troubles I'm having is that LVS of an openlane generated design fails. The problem seems to be due to mismatches parasitic diodes and not a "real" problem. However, it's still an LVS error and I really want to be able to LVS at the top level for obvious reasons. Do you know how I could make LVS pass for openlane generated modules? I believe openlane doesn't actually LVS at transistor level but as this an analogue flow I do want to LVS at transistor level. In case it's useful I've attached a test case where you can see the problem