Hi @User, I'm having a nightmare problem when instantiating more than one instance of a design in the top level wrapper: 1. Adding one instance of my design and wiring it up in

user_analog_project_wrapper.mag

and doing the same in the schematic

user_analog_project_wrapper.sch

passes LVS no problem. 2. Adding a second instamce of the sabe block in both the mag and sch without hooking up either causes LVS to fail! reporting one extra net and one extra device in the schematic as follows

Circuit 1: user_analog_project_wrapper_lvs |Circuit 2: user_analog_project_wrapper_lvs 
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (23)          |sky130_fd_pr__nfet_g5v0d10v5 (24) **Mismat 
sky130_fd_pr__pfet_g5v0d10v5 (43)          |sky130_fd_pr__pfet_g5v0d10v5 (43)          
sky130_fd_pr__cap_mim_m3_1 (2)             |sky130_fd_pr__cap_mim_m3_1 (2)             
sky130_fd_pr__pnp_05v5_W3p40L3p40 (6)      |sky130_fd_pr__pnp_05v5_W3p40L3p40 (6)      
sky130_fd_pr__res_high_po_5p73 (8)         |sky130_fd_pr__res_high_po_5p73 (8)         
Number of devices: 82 **Mismatch**         |Number of devices: 83 **Mismatch**         
Number of nets: 47 **Mismatch**            |Number of nets: 48 **Mismatch**            
---------------------------------------------------------------------------------------

I've tried literaly everything i can think of from re organising my folder structure to flattening all my sub designs before integrating them at the top and I have no idea whats going on. Does this info. give you any idea as to what might be happening?