Netgen seems to give me two sets of parameters for a single device in the schematic when running LVS (see below). The layout extracted FET has a width of

108

, but it's reporting the schematic FET to have two widths (circuit 2) one of

W=12

and another (same device)

W=96

, the sum of which is the expected

108

. The netlists being compared look sensible so I'm not sure whats happening. It's also worth mentioning that the problem doesn't arise when I run LVS on the layout of the block alone. Only when I run LVS on the wrapper containing only this block, vs. the wrapper schematic also containing only this block. Any ideas anyone? Netlists attached in case anyone can take a quick look. I know you're all also in a mad rush. Good luck and thanks!

Netlists match uniquely.
There were property errors.
sky130_fd_pr__nfet_g5v0d10v54 vs. ldo_ampI2/sky130_fd_pr__nfet_g5v0d10v5M9:
 w circuit1: 108   circuit2: 12   (delta=160%, cutoff=1%)
Circuit 1 parallel/series network does not match Circuit 2
Circuit 1 instance sky130_fd_pr__nfet_g5v0d10v54 network:
  l = 1
  w = 108
  ps = 0
  as = 0
  pd = 0
  ad = 0
  M = 1
Circuit 2 instance ldo_ampI2/sky130_fd_pr__nfet_g5v0d10v5M9 network:
  m = 1
  mult = 1
  sd = 0
  sb = 0
  sa = 0
  nrs = (expression)
  nrd = (expression)
  ps = (expression)
  pd = (expression)
  as = (expression)
  ad = (expression)
  nf = 2
  W = 12
  L = 1
  m = 1
  mult = 1
  sd = 0
  sb = 0
  sa = 0
  nrs = (expression)
  nrd = (expression)
  ps = (expression)
  pd = (expression)
  as = (expression)
  ad = (expression)
  nf = 16
  W = 96
  L = 1
Combined 8 parallel devices.
Combined 8 parallel devices.
Combined 2 parallel devices.
Result: Circuits match uniquely.
Property errors were found.