Thanks Russell for your response. I have two clocks DDRClkHS and ByteClkHS. The former's frequency is 4 times the later. Input bytes come with rising edge of the slower clock ByteClkHS. A counter counts with rising edge of the faster DDR Clock. When running simulation for long time 300 ns for example, the counter value is not zero when input byte arrived. It appears like Clock edge of faster clock shifts. How can I ensure that counter is zero when input byte comes ?? The module serializes 8 bit to 2 bit data. Thanks