Last 72 hours - Learn how to save gain and energy by 50% using CMOS Did you know, by just varying supply voltage across the inverter, you can actually achieve a huge gain and save power - all of it by more than 50%? Did you know CMOS robustness towards power supply variation makes it a good candidate for low power design? Do we still go for these configurations? If yes, why? If not, why? As I said, the above image is a classic VLSI interview question in top design companies including the ones which I have worked for. Interviewers can discuss the above image with you for close to an hour or more as the above CMOS characteristics form the fundamentals of low power design, physical design, STA and layouts. Learn some of the above core VLSI interview topics and many more by simulating them on VSD-IAT platform during the workshop using Sky130. 90% of participants who have done these workshops and completed all assessments/MCQs in 5-days are in some of the top companies you can think of. Without a doubt, this is one of the best chances you have to cover CMOS fundamentals which in turn will help in interviews. Above all of that, this is one of those workshops which is being recommended by industry Last chance - Registration closes in 72hours. Here's the link with more details- https://www.vlsisystemdesign.com/cmos-circuit-design-spice-simulation-using-sky130-technology/