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I'm going to be giving away some discount vouchers for my course on the 1st of December. If you're interested then join the mailing list here: https://www.zerotoasiccourse.com/newsletter/

Hi Everyone, I invite you to the IEEE Consultants’ Network of Northern New Jersey meeting with a presentation on Arduino PRO for Telecommunications, Internet of Things (IoT), and Industry 4.0 on Thursday, January 13, 2022 at 6:30 PM EST. Our speaker is Massimo Sacchi (@MassimoSacchi7) the Corporate Partnerships Manager at Arduino Pro. Please register to receive a link to the meeting.

VSD-HDP : Verilator Verification Environment for RISC-V vector accelerator Now this is how VSD wants to approach design verification - Something new, something exciting, something never done before - Probably, if you are reading this email and would be interested in joining our design verification HDP program, you would be the first one in the whole world (like all VSD interns in past) to do this, may be publish it. Reply back to this email, if you are interested, and we will send you registration/payment link Cohort Starting from Jan 15, 2022 for a duration of 10-weeks Big Picture: There has been, for about a year, an activity to try to work on a RISC-V vector accelerator that is tailored to be able to execute machine learning workloads. And there is one innovation that we are trying to do that nobody else in the world does and that is to implement an instruction called fused dot-product. A fused dot-product is a mechanism to introduce user-defined rounding in arithmetic. And if you do that, then what you gain is you are able to do smaller representations for the weights in the ML model. If we look at a traditional linear algebra execution engine, it will use a dot-product, but it will use a fused multiply-add. And if you do that then every sum of the “sum of products” that dot-product exists will have a rounding event. If we have a large matrix, which is typical in a machine learning environment, you have millions of rounding errors. And the reason this is a problem for machine learning is that the matrices that are being used are such that they tend to be multi-modal. What it really means (from a numerical point of view) is that you have multiple peaks of energy that you are trying to resolve. And if you have rounding error, you will have one of these peaks basically attenuate to a point where it is no longer resolvable This is what fused dot-product is solving From a verification point of view, the real fun starts in the fact that we are going to bring in different arithmetic. We could bring in IEEE, we could bring in bfloat from Google, we could bring Microsoft fp9 or we can bring in the number system called posit, which is a tapered floating point. There is research out there which people have done where they have demonstrated an 8-bit posit can compete with single precision IEEE floating point in these machine learning applications, if you use fused dot-product – That is the context of the project Project description: As you can imagine, there is close to 7000+ blocks that are of interest here that have their own complexity and need The project which we are starting here is really to try to build a testbench and verification strategy that would allow us to, progressively over time, add these blocks that are of importance We will start off with an integer ALU, not very much complexity in that, but it gives you a vehicle to start thinking about the whole verification strategy. One of the things we are trying to do is adhere to opensource strategy, so that anybody can pick up this GitHub repo and be productive with this, without needing industrial tools. And one vehicle which is industrial strength for verification is Verilator In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions. We can layer this testbench in such a way that when a new project resource comes online and needs to implement (for eg.) vector scale instruction, then there is a reusable testbench structure which that person can quickly pick-up, set as their basic structure, build their functionality into it, and have a working testbench environment in which they can test their work First Steps: First round of HDP will be a testbench which is driven purely by a C++ verilog testbench that brings in the golden model. This is the first step in which you take a verilog module that is a transformation of some sort, and you tie that into a Verilator testbench that can drive that module and that can also drive the golden result. So, this is Verilator specific in the sense that Verilator is really the main function of C++ program. And when you bring in a verilog module, that gets transformed into a C++ code that then gets driven by the main function of Verilator. There are 2 problem statements here One is to setup the environment so that you have the right Makefile, you have the right structure which you can expand to new functional units Second is how to link in the golden model     Summary of Project execution: 1.     Articulate a productive organization in which testbenches are built 2.     Then we need a productive Makefile that a programmer or designer can simply say “make test” and you have the test environment 3.     Then we need to have integration with the golden model which brings in new GitHub repo and that machinery needs to be figured out

Tapeout Program completes with STA workshop after 11 years It takes time to build anything great. We did run into obstacles, but quality of perseverance overcomes almost everything Building content for the "Tapeout Program" for the global semiconductor community really needed a good team of passionate industry leaders who are not only experts in their domain, but also share a similar vision. It is easy to find STA engineers, but (and this "but" comes with capital "B") it's really challenging to find STA leaders. Though I had enough experience doing STA in my previous jobs from device physics point of view, VSD needed to be fair with the community for such an important topic and decided to look for trusted partners.     VSD got lucky once again to have met Vikas Sachdeva - VLSI coach, trainer, Innovator, Speaker, Bachelor's from IIT Delhi and moreover an amazing human being. He got 8 publications and 2 patents under his belt. Vikas runs a very popular website "*vlsideepdive*" where he is an advisor for early stage products, courses, driving innovation in edtech, learning methods, professional training and coaching VSD is really glad to announce the next workshop with Vikas on "*Sign-off Timing Analysis - Basics to Advanced*" from 2nd to 6th Feb, 2022. The Indian government is pushing hard to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a Semiconductor ecosystem that requires 85,000+ highly trained engineers. This engagement with Vikas is just the beginning of a long term relationship and we plan to work together deeply on Next gen VLSI EdTech which would cater to the needs of Indian semiconductor ecosystem Take a look at "Workshop Content" in below link. All the best and happy learning https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/

Upcoming Sign-off STA 5-day workshop and its benefits Answers to general FAQs about the upcoming Sign-off STA 5-day workshop - Its for a different set of students and professionals, who are currently studying STA from YouTube and Udemy, but looking for some valid, more robust lab based certification to apply for STA jobs OR are planning to switch to STA roles in their profession. You can think of this workshop as a guided STA Masterclass which has all necessary information (through lab work) to sign-off a chip tapeout. This workshop will compel you to write constraints and test them on your design during lab sessions. Currently we are using OpenTimer for labs as we have done entire survey of opensource tools for STA and OpenTimer offers the perfect flexible solution especially for STA learning (especially timing graphs), as you can write commands at core STA engine  Post this workshop, learning any commercial grade STA tools will become a cake-walk, as would be explained by the instructor himself during the workshop. And most importantly - your certificates and lab reports will be circulated to all my industry members who are looking for STA engineer recruits. Your Workshop lab account and GitHub report will make ensure to your interviewer that you got the concepts right and are ready to get absorbed So all the best and I will see you during the workshop Here's the link to register- https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/

2 unique programs catering to next-generation VLSI recruits Program 1 – VSD-HDP (10-weeks from Jan 29 onwards) Link to register - ONFI Compliant NAND flash controller (Project code : ONFI) What is a NAND flash controller? Basically, when you have storage media like USB sticks or SSDs, they consist of interfaces like USB, NAND flash controllers and an actual flash, which stores the actual data. So, the NAND flash controller is responsible for the interface between your computer and actual flash storage chips. NAND flash controllers can have different interfaces, so they can interface with 1/8/16 flash chips. Even in SD cards, you have small controller inside it, and it’s interconnected with the flash inside SD cards So, flash controllers are needed in all kinds of storage devices Now what does the flash controller look like? What are they doing? For example, typical flash controller consists of CPU, it has some RAM/ROM, it has a DMA engine which is responsible for transferring data, then there is a NAND flash controller which optionally has ECC for error correction of the flash, its connected to actual flash chip, usually outside of the controller The flash controller uses the ONFI flash protocol which is an effort for standardizing the communication protocol between NAND flash controller and actual flash Let’s take a deeper look into the flash controller – it reads and writes content from small RAM, it has control registers, it has ECC for error correction and NAND flash interface then talks to NAND flash memories which are usually separate IP requirements: ·       ONFI compliant minimum 3.1 ·       An ECC core is optional, we could do that in software ·       Minimum 1 flash channel, optionally up to 16 channels, preferably configurable ·       Language: Verilog 2005 or TL-Verilog ·       Target Platforms o  FPGA ICE140 – IceStick/IcoBoard o  ASIC – Skywater 130nm PDKs Program 2 – VSD-IAT (5-days from Feb 2 onwards) Link to register - Sign-off Static Timing Analysis – Basics to Advanced Really glad to conduct a 5-day lab intensive Sign-off Timing Analysis workshop with Vikas Sachdeva . It really needs an open-mindedness to adapt to a more effective form of cloud lab-based learning. Open-minded participants who have completed similar workshops in the past are doing very well in industry as it needs utmost sincerity, smart-work and hard-work to complete a 5-day workshop with a lab score of above 80%. This format brings the best out of your technical and managerial abilities, which is a very important skill needed by industry Times have changed, and the industry is looking for candidates who are open to all kinds of challenges presented to them. So, all the best, give your best and notice the change for yourself All the best and happy learning

LAST 24-hrs RTL design/synthesis workshop using sky130 - This time with an industry connect As per heavy demand from industry and students across globe, restarting workshop series, with RTL design and synthesis using verilog and sky130 5-day workshop, whose registration closes in 24-hours from now Participants who complete this workshop with valid lab document are directly eligible for our next round of 3-months advanced industry grade programs in association with some top design and service companies, with placement guidance. This is a great opportunity coming straight from industry to VSD to send good talent. So all the best, do well and I will see you in workshop Here's the registration link https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/

Cloud FPGA workshop in VSD style First let me tell you why we are doing this? Because of you, our students, our global participants, our corporate customers. About a year back, we were introduced to existing FPGA training programs in colleges and institutes. VSD analyzed the content and it looked quite common across all institutes VSD had to differentiate and restructure the entire content, and it took close to 8-months of planning, recording and building the entire cloud platform for global students. If you closely look into FPGA programming methodology for any board, the fundamentals are same. Its the FPGA fabric which plays a crucial role while deciding on number of LUTs, performance, area, power. So this short 5-day workshop purpose to create an awareness about, FPGA fabrics and its relevance in FPGA programming, thereby opening new opportunities, especially for freshers, looking for core FPGA jobs and projects Really Thankful to Prof. Nanditha Rao and Dr. Xifan TANG from Open-Source FPGA Foundation for being the torch bearer of this initiative. Also thankful to Hugo A. Andrade and Parimal Patel from Xilinx who have been very helpful from day 1 when we planned this workshop. All of them are examples of courageous and dedicated leaders who look differently at future of Semiconductor industry I am sure, this project, this workshop and this team is just the beginning of a bigger mission to make each country build their own FPGA fabrics and hence their own FPGA boards Here's the registration link with more details. Stay tuned for more posts about this workshop https://www.vlsisystemdesign.com/fpga/

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Why settle for less, when you can get more in 5-days? Now me and my team did a quick research. We haven't seen any FPGA coursework which gives lab based overall view about FPGA design, architecture and fabric The distinct fundamental differences between FPGA IP designer and FPGA application designer (which are 2 job roles by itself) needs to come out with labs that will help community to choose the right career path Looking forward to interact with FPGA beginners and experts through this workshop, and plan good research projects in areas of FPGA design, Fabric and architecture Here's the registration link https://www.vlsisystemdesign.com/fpga/

And the countdown begins - Registration for FPGA closes in 4-days Registration link - https://www.vlsisystemdesign.com/fpga/ Workshop Day-wise content is here Day1: 1. Introduction to FPGA 2. Counter example using Vivado 3. Counter Verilog explanation and implementation using Vivado 4. Vivado timing, power, and area measurement for counter 5. Introduction to VIO Day2: 1. Introduction to OpenFPGA and VTR (verilog-to-routing) 2. Introduction to VPR (versatile-place-and-route) using basic Earch fabric 3. Counter example using VPR/VTR openfpga flow Day3: 1. Introduction to basic RISC-V core – rvmyth 2. Rvmyth – Vivado RTL to synthesis flow 3. Rvmyth – Vivado Synthesis to bitstream Day4: 1. Introduction to opensource SOFA FPGA fabric 2. Steps to run counter example on SOFA 3. Characterize counter example in terms of area and timing 4. Post-implementation netlist and simulation using SOFA Day5: 1. Steps to run RISC-V Core - on SOFA 2. Characterize RVmyth in terms of performance and area 3. Steps to generate rvmyth post-implementation netlist 4. Confirm RVmyth on SOFA behavioral simulation using Vivado

[Last 2 days] FPGA power, performance, area analysis There is a reason why our seniors have been asking us to focus on fundamentals rather than tools. Fundamentals of an FPGA power, performance and area analysis is very similar to that of an SoC. Techniques to measure them are tool dependent. VSD team has an advantage of having SoC and Embedded background, which helped to compare both flows in terms of time-to-market and PPA There are many such interesting details (including the above one) being covered as a part of an upcoming FPGA workshop. This is one of its kind, state-of-the-art workshop, where we are not only just building applications using Xilinx Basys boards, but we are entering into FPGA chips and exploring what exactly is happening there, from SoC point of view Registration link (Last 2 days) https://www.vlsisystemdesign.com/fpga/ Your FPGA journey doesn't end there. We are planning some cool (paid) hardware design programs in and around FPGAs with our OpenFPGA partners. Planning is underway. Stay tuned. All the best and happy learning

If you are an ASIC or Physical Design engineer, you will be so amazed to know about the similarities between FPGA and ASIC PNR flow. Fundamentals remain so same, just different modes of configuring 2 different systems I am very sure, after this workshop, all of you Physical Designers will question - why haven't we explored FPGAs before? If you have an RTL, and want to quickly check its performance on real hardware, FPGA is the way to go about Here's the registration link [Valid for last 15hrs] https://www.vlsisystemdesign.com/fpga/ All the best and I will see you in workshop

New Projects on HDP (starting on 27th March) Project Name (Digital design and Synthesis) - Enabling SDC switches in Yosys using SKY130 (Project code - ESSY) Project description - Yosys is an open source logic synthesis tool . Unfortunately there is no support for the regular SDC in Yosys. The aim of the project is to take certain specific constraints in SDC like set_max_delay , set_input_delay , set_input_transition , etc and enable the equivalent features in Yosys by creating custom synthesis scripts. The scope of this project gives a very good exposure to Verilog coding skills, Working of synthesizer, Logic optimization knobs in logic synthesis, Design constraints Project Name (analog design) - High Frequency analog VCO design and implementation using Sky130 (Project code - KCEDVCO) Project description - 200MHz, 400MHz and 915MHz VCO design using Sky130nm - from specification to tapeout Project Name (analog design) - Circuit Design for Capacitive Sensing - Touch/Pressure using SKY130 (Project code - CDCST) Project description - The capacitance to digital converter (CDC) are being extensively used in Biomedical diagnostics, Water and level sensing applications in Industrial sector, MEMS sensor interface and plenty of hobby projects by young engineers. The basics of capacitance sensors, types of cap sensors - Floating and Grounded and their construction is discussed. Learn about the interdigitated Capacitor platform for many Gas Sensing applications and pressure sensing applications. VSD-HDP - link https://www.vlsisystemdesign.com/hdp/

Keep a note of all VLSI learning options available by VSD Not sure if everyone knew about our other free and low cost learning options. The FREE and Udemy ones are also so well documented, that we have seen many candidates using them for job interviews few years back. Now you have all resources which will help you to chose VLSI hardware career over software jobs 🙂 Free, self learning - Pick one project and perform all steps given in GitHub under below link https://www.vlsisystemdesign.com/ip/ Udemy (less paid) is theory+labs, which you need to do with self-learn. Order in which you need to take the courses is given in below link under my bio https://www.udemy.com/user/anagha/ There are workshops (mid-range fees), which you quickly ramp up with labs which currently are being used in industry, but with opensource https://www.vlsisystemdesign.com/vsd-iat/ There is hardware design program (expensive) which is lab intensive, mentor based, 10-weeks, which can improve your chances of placement and jobs in top design and service companies https://www.vlsisystemdesign.com/hdp/ Now depending upon your budget and how fast you want to ramp up in semiconductor, you can choose and go for it. Also, before choosing any option, check equivalent course market price and compare

Month end $5/$9 or Rs.360/Rs.700 courses are back for Last 14hrs to get all my online VSD-VLSI courses for $5/$9 or Rs.360/Rs.700 each based on your location Sharing Tips again Tips on order in which you need to learn VLSI and become a CHAMPION (especially for students/freshers): If I would had been you, I would had started with Physical Design course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built. Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses. And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle Now once my fundamentals are cleared and if I want to learn RTL and synthesis, from specifications to layout with a example design, I will go in below order (Only after I finish all above courses): 1. RISC-V ISA course Part 1a and Part 1b will teach the best way to define specs for a complex system like microprocessor 2. Then I will go for RISC-V Pipeline RTL design 3. Next would go for RISC-V SoC Design which involves SoC planning and integration 4. Finally I would go for RISC-V physical design and Layout All VLSI courses using FPGAs and Skywater 130nm PDKs done by VSD-HDP Interns are below VSD – Mixed signal RISC-V based SoC on FPGA https://www.udemy.com/course/vsd-mixed-signal-risc-v-based-soc-on-fpga/?couponCode=B7660FE44C49D51D509E VSD Intern – Mixed Signal Physical Design flow with OpenLANE/Sky130 https://www.udemy.com/course/vsd-intern-mixed-signal-physical-design-flow/?couponCode=5B03AA9D084922BDBD34 VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130 https://www.udemy.com/course/vsd-intern-openram-configuration-for-4kb-sram-using-sky130/?couponCode=DFF67B18521CC9F5FBA4 VSD Intern – Analog Bandgap Reference design usingSky130 https://www.udemy.com/course/vsd-intern-analog-bandgap-reference-design-using-sky130/?couponCode=831B0E2FD347A3AABC16 VSD Intern – Analog comparator design usingSky130 https://www.udemy.com/course/vsd-intern-analog-comparator-design-using-sky130/?couponCode=F2BC16263B87BB3B555A VSD Intern - DAC IP design using Sky130 PDKs - Part 1 (specifications) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-1/?couponCode=0558063C3ECDEF3EC36F VSD Intern - DAC IP design using Sky130 PDKs - Part 2 (circuit design) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-2/?couponCode=6764CDF3D0886B26D163 VSD Intern - DAC IP design using Sky130 PDKs - Part 3 (layout) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-3/?couponCode=3AB4AD87B6DCA411EC09 VSD Intern – 10-bit DAC design using eSim and Sky130 https://www.udemy.com/course/vsd-intern-10-bit-dac-design-using-esim-and-sky130/?couponCode=C76E17176C948FAC744A Connect with me for more guidance !! Hope you enjoy the session best of luck for future

An amazing evening spent with VSD-HDP success story on RISC-V Tensorcore. For more details on how to do this project as a part of VSD Hardware design program (HDP), refer to below link. https://www.vlsisystemdesign.com/hdp/ Many participants have rapidly decided to take up HDP programs and are getting skilled/placed without wasting any time. VSD interns are in huge demand within semiconductor product and services companies Here's next VSD-HDP success story webinar on "*High Speed VCO Design and Tapeout in Skywater 130nm Technology*" is scheduled on 12th April, 8pm IST. Use below link to register https://www.vlsisystemdesign.com/vsd-intern-free-webinar/ More details about the webinar speakers and mentors coming soon. Stay tuned All the best and happy learning

Know Your Founder from Chipspirit As you all might know, we are conducting a 5-day RTL design and Synthesis workshop using SKY130 and the top 10 participants will be hired by Chipspirit. This workshop is (for the first time) discounted by 59% in the spirit of hiring great top 10 engineers. While you enroll for this workshop, it's very important for you to know a bit about the founder of Chipspirit. Why so? Because your future career will be shaped based on the vision of your founder, and based on how focused your founder is (A little secret - When I had got my first job at Qualcomm, I had also researched a bit about Irwin Jacobs) While the above image highlights a bit about Chipspirit founder - Mohan Jindal, I would like to give some more info - He has 21 years of experience in VLSI developments, and he has contributed to 30+ silicon tape outs. Mohan left Intel and started Chipspirit in 2018. During his career he earlier worked with LSI, Atmel, and Freescale on chip developments for security, Xeon-Servers, and IOT applications. Mohan completed M.Tech from IIT Kharagpur in Microelectronics and VLSI Design and B.Tech. from CRSCE, Murthal More importantly - He loves "Make In India" If you ask any expert from the VLSI industry, you will get a similar response that working for a product start-up at the initial phases of your career is a really great idea and Chipspirit has it all Here are the 5-day workshop details - https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/ All the best and happy learning

I’m excited to report receipt my Certificate of Completion for attending the Skywater 130nm Advanced Process Design Workshop held August 2-8, 2022 from the VSD-IAT. To learn more about the workshop, please see my blog and report on GitHub

Did everyone see @Matt Venn's TinyTapeout project? https://mailchi.mp/574276e3c9d7/tinytapeout?mc_cid=28ec6db3c0&mc_eid=d16f71268b

Why Analog HDP? Why SKY130? Why Now? Because they are in demand - all the time Hi There, When we started our full-fledged open-source EdTech platform in 2017, using OSU180nm, the most common and popular questions among freshers and non-backend engineers were First - What is the difference between macros and IPs? Though, theoretically, everyone can answer this question with decent images, but (with capital B), unless we make them build IPs, this question keeps coming up. While others could answer this query over WhatsApp and Telegram in a few minutes, we took 18 months to answer this query. So did we answer this query? By building analog IPs using educational OSU180nm PDKs Next - What is a PDK? Again, the answer can be beautifully articulated by industry experts over WhatsApp and Telegram, but (with capital B), unless we make them use real PDKs, this question keeps coming up. That was the year when Google+SKY130 launched completely open source PDKs, which were used to build analog IPs through hand-curated VSD IP design HDP programs. Result - We handled this question too, by making students open the PDKs using an editor and use them for analog IP design We hit jackpot when we built our own SoC using our own built analog IPs, which made participants very comfortable understanding PDK and IP As I said, analog is in demand - all the time. Launching the next analog HDP program on September 3. Registration closes in 5 -days. Here's the link https://www.vlsisystemdesign.com/hdp/ Below are the top 4 analog HDPs using SKY130 under the guidance of industry analog experts. All the projects lead to guaranteed attention by the industry, as per our experience 1. 10-bit Potentiometric DAC 2. High-frequency analog VCO design 3. Low dropout regulator - LDO 4. Circuit design for capacitive sensing All the best and happy learning

Hi everyone, I invite you to join the IEEE Consultants’ Network of Northern New Jersey meeting on an Introduction to Mechanical Design Using FreeCAD by George Vella-Coleiro on Thursday, September 22, 2022 from 6:30 PM to 8:30 PM followed by a networking session on Zoom. Please register to receive a Zoom link to the meeting.

Dear all, As part of the AC3E/Chile Chipathon project, I've made this video tutorial about the basics of hierarchical LVS using xschem and MAGIC, including practical aspects and frequent issues when you face it for the first time. The video is in spanish, intended to help the spanish-speaking community to get involved with opensource IC design tool, but it has english subtitles loaded (use caption option in YouTube). I really hope you find it useful! And please let me know if you have any comments or suggestions. @User @User @User @User @User Posted in #analog-design

Hi everyone, I invite you to join the IEEE Consultants’ Network of Northern New Jersey meeting on Open Source Chip Design with Dr Mehdi Saligane on Thursday, October 27, 2022 from 6:30 PM to 8:30 PM followed by a networking session on Zoom. Please register to receive a Zoom link to the meeting. https://events.vtools.ieee.org/m/328096

https://github.com/bmurmann/Book-on-MOS-stages looks pretty cool

looks like lots of good stuff here: https://www.metis4skills.eu/curriculum-courses/

Hi everyone, I invite you to join the IEEE Consultants’ Network of Northern New Jersey meeting on Communications and Networking in LEO Mega-Constellations by Gunes Karabulut Kurt on Thursday, February 16, 2023 from 7:30 PM to 9:30 PM followed by a networking session on Zoom. Please register to receive a Zoom link to the meeting. https://events.vtools.ieee.org/m/342993

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