03/17/2022, 2:27 AM
And the countdown begins - Registration for FPGA closes in 4-days Registration link - Workshop Day-wise content is here Day1: 1. Introduction to FPGA 2. Counter example using Vivado 3. Counter Verilog explanation and implementation using Vivado 4. Vivado timing, power, and area measurement for counter 5. Introduction to VIO Day2: 1. Introduction to OpenFPGA and VTR (verilog-to-routing) 2. Introduction to VPR (versatile-place-and-route) using basic Earch fabric 3. Counter example using VPR/VTR openfpga flow Day3: 1. Introduction to basic RISC-V core – rvmyth 2. Rvmyth – Vivado RTL to synthesis flow 3. Rvmyth – Vivado Synthesis to bitstream Day4: 1. Introduction to opensource SOFA FPGA fabric 2. Steps to run counter example on SOFA 3. Characterize counter example in terms of area and timing 4. Post-implementation netlist and simulation using SOFA Day5: 1. Steps to run RISC-V Core - on SOFA 2. Characterize RVmyth in terms of performance and area 3. Steps to generate rvmyth post-implementation netlist 4. Confirm RVmyth on SOFA behavioral simulation using Vivado