03/31/2022, 2:18 PM
Month end $5/$9 or Rs.360/Rs.700 courses are back for Last 14hrs to get all my online VSD-VLSI courses for $5/$9 or Rs.360/Rs.700 each based on your location Sharing Tips again Tips on order in which you need to learn VLSI and become a CHAMPION (especially for students/freshers): If I would had been you, I would had started with Physical Design course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built. Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses. And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle Now once my fundamentals are cleared and if I want to learn RTL and synthesis, from specifications to layout with a example design, I will go in below order (Only after I finish all above courses): 1. RISC-V ISA course Part 1a and Part 1b will teach the best way to define specs for a complex system like microprocessor 2. Then I will go for RISC-V Pipeline RTL design 3. Next would go for RISC-V SoC Design which involves SoC planning and integration 4. Finally I would go for RISC-V physical design and Layout All VLSI courses using FPGAs and Skywater 130nm PDKs done by VSD-HDP Interns are below VSD – Mixed signal RISC-V based SoC on FPGA VSD Intern – Mixed Signal Physical Design flow with OpenLANE/Sky130 VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130 VSD Intern – Analog Bandgap Reference design usingSky130 VSD Intern – Analog comparator design usingSky130 VSD Intern - DAC IP design using Sky130 PDKs - Part 1 (specifications) VSD Intern - DAC IP design using Sky130 PDKs - Part 2 (circuit design) VSD Intern - DAC IP design using Sky130 PDKs - Part 3 (layout) VSD Intern – 10-bit DAC design using eSim and Sky130 Connect with me for more guidance !! Hope you enjoy the session best of luck for future
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