This is liable to be a very rookie mistake but has anyone here successfully synthesized a design with the stdcells through Genus? I'm using the

*.magic.lef

files in the PDK along with the corresponding tech LEF. I'm loading the .lib and the technology+cell LEFs in my synthesis script:

set_db library ${LIBFILE}
read_libs ${LIBFILE}
set_db lef_library [concat ${TECH_LEF} ${CELL_LEF_LIST}]

but attempting to synthesize a design results in a plethora of library warnings related to timing arcs:

Warning : Detected both combinational and sequential timing arcs in a library cell. This might prevent the tool from using this cell for technology mapping. The tool will treat it as unusable. [LBR-76]
        : The arc 'CLK_GATE_Ha0' between pins 'CLK' and 'GATE' in libcell 'sky130_fd_sc_ls__dlclkp_1' is a sequential timing arc.

as well as issues with inconsistent naming between the .lib and the LEF files:

Warning : Pin names are not consistent in lib and LEF files. [PHYS-113]
        : Pin 'VNB' of library cell 'sky130_fd_sc_ls__nor4_2' is in logical library but not in physical library.

as well as issues with missing via information:

Info    : Via with no resistance will have a value of '0.0' assigned for resistance value. [PHYS-129]
        : Via 'M3M4_PR_MR' has no resistance value.

Can anyone provide some insight into where I'm going wrong?