open-source-silicon #stdcelllib

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Philipp Gühring

07/19/2020, 5:10 PM

Workshop is starting: https://meet.jit.si/Sky130lclayout

Michael Stetzler

09/21/2020, 5:48 AM

@User has left the channel

Remy Prechelt

09/27/2020, 8:36 AM

This is liable to be a very rookie mistake but has anyone here successfully synthesized a design with the stdcells through Genus? I'm using the

*.magic.lef

files in the PDK along with the corresponding tech LEF. I'm loading the .lib and the technology+cell LEFs in my synthesis script:

set_db library ${LIBFILE}
read_libs ${LIBFILE}
set_db lef_library [concat ${TECH_LEF} ${CELL_LEF_LIST}]

but attempting to synthesize a design results in a plethora of library warnings related to timing arcs:

Warning : Detected both combinational and sequential timing arcs in a library cell. This might prevent the tool from using this cell for technology mapping. The tool will treat it as unusable. [LBR-76]
        : The arc 'CLK_GATE_Ha0' between pins 'CLK' and 'GATE' in libcell 'sky130_fd_sc_ls__dlclkp_1' is a sequential timing arc.

as well as issues with inconsistent naming between the .lib and the LEF files:

Warning : Pin names are not consistent in lib and LEF files. [PHYS-113]
        : Pin 'VNB' of library cell 'sky130_fd_sc_ls__nor4_2' is in logical library but not in physical library.

as well as issues with missing via information:

Info    : Via with no resistance will have a value of '0.0' assigned for resistance value. [PHYS-129]
        : Via 'M3M4_PR_MR' has no resistance value.

Can anyone provide some insight into where I'm going wrong?

Elkim Roa

11/12/2020, 3:23 AM

@User has left the channel

Nguyen Dao

05/08/2021, 9:56 AM

Hello all, has anyone done or known whether we can generate a liberty file (.lib) for a custom cell using an opensource tool?

Tim Edwards

05/08/2021, 4:29 PM

@User: The best person to ask is @User.

👍 1

Teo Ene

05/08/2021, 4:53 PM

I was unable to find any modern open-source characterization tool when I checked. However, characterization is just a matter of running multiple spice simulations. It can be done by hand. And it can also be automated, should one have the time to do so. Characterization tools like Liberate are not complicated, they are just large in scope. Creating an open-source variant is a reasonable undertaking.

👍 1

Philipp Gühring

05/09/2021, 9:36 AM

@User There are currently 2 OpenSource characterization tools: lctime from librecell https://codeberg.org/tok/librecell/ and https://www.vlsisystemdesign.com/ip/ (which I havent tested yet)

Philipp Gühring

05/09/2021, 9:37 AM

I am using lctime in my Standard Cell Library Generator:

Philipp Gühring

05/09/2021, 9:37 AM

https://github.com/thesourcerer8/StdCellLib

👍 1

Philipp Gühring

05/09/2021, 9:38 AM

You can see examples that were generated here: https://pdk.libresilicon.com/dist/StdCellLib_20201106_SKY130/Catalog/buildreport.html

Nguyen Dao

05/09/2021, 9:52 AM

@User great! Thanks for the info.

FatsieFS

05/10/2021, 3:24 PM

@User @User: LIP6 has a static timing analyser that can also be used to generate liberty files for cells and macro blocks: https://www-soc.lip6.fr/en/team-cian/softwares/tasyagle/. They simplified transistor models for digital timing simulation so it should be faster than ngspice. The public downloadable version is currently not under an OS compliant license but LIP6 will relicense it under GPL. They did not find the time yet to do the License change in the source code.

James Stine

05/10/2021, 3:25 PM

@User Right now we use liberate from CDS for generating liberty files. You are welcome to try it and correlate the numbers versus ours. We might get time to check them but have other things on our list. Any collaboration would be appreciated - thanks!!!!!

FatsieFS

05/10/2021, 3:33 PM

@User Good, after they release their open source version of the software I'll try to get both of you to connect to see if there could be collaboration. I don't necessarily need to be in the loop.

James Stine

05/10/2021, 3:35 PM

@User That’s fine - we are committed to open-source but for now use the commercial tools to validate the open-source ones. I did indicate to Google that I will write an open-source characterizer using Python when I get some time. But, we are confident that are our numbers are good — btw, our characterization uses full extraction so that would have to be utilized if you want to do a fair comparison.

yrrapt

06/22/2021, 6:54 PM

@User if I wanted to have a play with StdCellLib would I be better to clone your fork or the original chipforge repo? There seems to be quite some divergence in commits:

This branch is 239 commits ahead, 141 commits behind chipforge:master.

Philipp Gühring

06/22/2021, 7:10 PM

If you are interested in Popcorn, which grows cell netlists out of a single inverter netlist, take a look at the chipforge repo, Hagen told me that he tried to improve it lately but I havent had the time lately to catch up with it. If you want to get cell netlists to build a complete cell library, use my repo.

Philipp Gühring

06/22/2021, 7:10 PM

I tried to keep them the repos in sync for quite some time, but at some point that just wasnt feasible anymore.

yrrapt

06/22/2021, 7:55 PM

Great, thanks. Unfortunately neither seem to be working quite right for me with

make catalog

I will see what I can track down.

yrrapt

06/22/2021, 7:55 PM

!! insane cell-inputs check ()
!! insane cell-outputs check ()
!! insane cell-netlist check ()
*** ERROR: vector required, but got ()
Stack Trace:
_______________________________________
  0  (vector-ref mosfet |gate-node#|)
        at "../Tools/popcorn/popcorn-lib.scm":608
  1  (mosfet-gate mosfet)
        at "../Tools/popcorn/popcorn-lib.scm":2216
  2  (complementary-mosfets netlist anchor)
        at "../Tools/popcorn/popcorn-cell.scm":1095
  3  (cell:expand-nor (cell:read-file cell-file) stacked-limit buf ...
        at "../Tools/popcorn/popcorn.scm":393
  4  (cell:write-file (cell:expand-nor (cell:read-file cell-file)  ...
        at "../Tools/popcorn/popcorn.scm":393
make[1]: *** [<http://stacked2_cells.mk:122|stacked2_cells.mk:122>: OOAI22] Error 70
make[1]: Leaving directory '/home/tom/repositories/StdCellLib/StdCellLib/Catalog'
make: *** [GNUmakefile:126: catalog] Error 2

yrrapt

06/22/2021, 7:56 PM

#    _ __   ___  _ __   ___ ___  _ __ _ __
#   | '_ \ / _ \| '_ \ / __/ _ \| '__| '_ \\
#   | |_) | (_) | |_) | (_| (_) | |  | | | |
#   | .__/ \___/| .__/ \___\___/|_|  |_| |_|
#   |_|launched:|_| 20210622
../Tools/popcorn/popcorn -b 5 -D "2-input Not-OR (or NOR) gate" -m nor -c NOR2 INV > NOR2
*** ERROR: unbound variable: grep-highest-internal-node
Stack Trace:
_______________________________________
  0  (grep-highest-internal-node netlist)
        at "../Tools/popcorn/../popcorn/expander.scm":397
  1  (grep-highest-internal-node netlist)
        at "../Tools/popcorn/../popcorn/expander.scm":397
  2  (expand-netlist-nor current-netlist)
        at "../Tools/popcorn/../popcorn/expander.scm":452
  3  (expand-cell (common:dataset-cell cell-file) expansion-method ...
        at "./../Tools/popcorn/popcorn.scm":319
  4  (exporter:dataset-cell cell)
        at "./../Tools/popcorn/popcorn.scm":321
  5  (rdisplay (exporter:dataset-cell cell))
        at "./../Tools/popcorn/popcorn.scm":321
make[1]: *** [<http://stacked2_cells.mk:118|stacked2_cells.mk:118>: NOR2] Error 70
make[1]: Leaving directory '/home/tom/repositories/StdCellLib/chipforge/Catalog'
make: *** [GNUmakefile:112: catalog] Error 2

Philipp Gühring

06/23/2021, 5:06 PM

Try to run them several times, sometimes that helped for me.

❤️ 1

Philipp Gühring

06/23/2021, 5:10 PM

There are actually 3 different popcorn variants: The first one was in TCL by Hagen (Tools/tcl/popcorn), the second one was in Scheme by Hagen (Tools/popcorn/) and the third one I developed in Perl (Tools/perl/popcorn) but that one had a different approach, it just tried to generate all possible netlists, it didn't "grow" them.

💯 1

Philipp Gühring

06/23/2021, 5:13 PM

Well, and there was a fourth try where I tried to grow it automatically, which is called "kino", but it isn't complete yet, and it's based on the TCL one from Hagen.

hamza shabbir

06/25/2021, 3:59 PM

@User has left the channel

Ramesh Sagi, Std Cell, Cadence SKILL

10/22/2021, 1:43 PM

Ted

12/04/2021, 5:15 PM

@User has left the channel

Matt Venn

09/25/2022, 9:49 AM

@Matt Venn has left the channel

Anagha

12/19/2022, 8:12 AM

@Anagha has left the channel