I ve even see a risc v core that retires 2 instructions per open-source-silicon.dev #openram

I've even see a risc-v core that retires 2 instruc...

tnt

07/30/2020, 6:54 PM

I've even see a risc-v core that retires 2 instructions per cycle and uses a 2 W + 4 R register file.