Hi Guys , We , the MERL team (www.merledupk.org) are trying to use OpenRAM generated SRAM IP (64 KByte) with our RISC-V, 5-stage pipeline core using TL-UL bus. The paper related to Open RAM (OpenRAM: An Open-Source Memory Compiler in ICCAD 2016) by @User and team, says that there is a bi-directional data bus for read and write. I want to ask, if there is any latest development with OpenRAM generated SRAM IP with provision of separate read write port for data bus?