@User This is interesting. I have been working on this exact idea for some time to address the SRAM issues in Caravel. At the moment, I am generating 1Kbyte block (256x32) and the initial results are promising. This memory uses a custom placer and (maybe a custom router) based on OpenDB APIs. The end goal is to develop this further to have a standard cells SRAM/RegisterFile/Cache compiler. Here are the initial results: