So, we're getting further with the Edalize backend for openlane and I'm hoping to start looking at adding OpenRAM instances soon. I'm still very new to the ASIC flow world so one very basic question to begin with. What output files from the OpenRAM compiler are going into the flow? From the limited testing that @User and I have done for simple test designs it seems we need at least a verilog blackbox + a LEF file, but I have a hunch that there could be more things