I have a question regarding reading and writing to the same address in a dual ported RAM at the same cycle. It is very relevant for my design. The OpenRAM Documentation says: Reads and writes on multiple ports to the same address in the same cycle “feed through” but the noise margins of the bitcell must be able to handle this. whereas the verilog model gives you a warning: if (!csb0 && !web0 && !csb1 && (addr0 == addr1)) $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1); So is it save to disable the warning ? Thank you for yuor help in advance. Cheers, Tobias