Hi @User, I have a weird problem, and I’m sure you can help me. I need to define the execution frequency of the design in order make the relevant adjustments in the logic. The concept won’t work when running it slower. And of course it should be maximal. The critical path is an SRAM read, and it is my understanding, that this depends on the clock-high-time. Since this cannot be characterized right now we need to rely on the simulation. Do you know this value ? I only identify clock rise\fall constraints in the lib file. My plan is to use caravan to have more flexibility with tweaking the design clock (estimated 150MHz) and to create a proper test environment. I offer to test and report on “my” clock-high-time if everything works out fine. Thank you for your reply in advance, Cheers, Tobias