How are the wire delay compared to gate delay "in general" ? I know this is broad, but like in FPGA the routing length is on the same order of magnitude as the actual logic delays. I have no idea in a 130nm ASIC how long it takes a signal to go from A to B. (then of course longer wire means higher capacitance which will also slow down the gate ... again, no idea of what range we're in here. Liberty files seems to have specs for up to 1.5 pF load capacitance)