@User: We have been preparing for fab a number of designs including a RISC-V processor (simple picorv32), SRAM, and padframe, for the purpose of making sure that we understand the process and the tool flows. These will go into fab soon, and we should have them back soon enough to make sure that we have identified and fixed any problems that would otherwise get duplicated in the harness design. We are starting on the definition of the "harness" padframe for customer designs. Documentation will be made available once we have the harness defined, which we will want to be done no later than a month (and hopefully sonner), as these will be critical for anyone wanting to meet the (also as-yet unspecified) deadline for the November tapeout. For the moment, you can assume that the general statements about the harness, such as the area available, availability of a RISC-V processor, memory block, and wishbone bus, are all true.