Teaser: I am preparing a handful of examples of analog, digital, and full-chip flows with the Google/SkyWater PDK on opencircuitdesign.com . They will go up once the requisite files (padframe I/O library, device models) are in the Google/SkyWater repository. Meanwhile, just to prove that the I/O library is not vaporware, here is a plot of a simple (unwired) chip design that I ran through the floorplanner app in https://github.com/RTimothyEdwards/open_pdks (common/soc_floorplanner.py, a variant of which I think is being used in openlane):