The plan for the harness is still to use picorv32, correct? I actually extended and early version of this core in 2016/2017 with a RISC-V Debug Spec (version 0.9) JTAG debug interface and extended the interrupt controller with a priority encoding scheme. I even taped out that core in both 12nm (clock rate 1GHz) and 16nm (clock rate 250MHz). Will the core in the harness have any debug capability, or just "printf" debugging?