: No, this is intentional behavior. The well and substrate connections in the standard cells (except HVL) are not connected to any metal. Therefore LEF cells that have the VNB and VPB pins on LI1 are just plain wrong, and since they are in positions that collide with the power supplies on LI1 in the same position, they are doubly wrong. I corrected the LEF (both the standard cell views and the technology LEF files for each standard cell set), and to my understanding, they are now correct with respect to the nwell/pwell layers and the VNB/VPB pins. Unless I have done something wrong with the syntax, or unless the PDK has ended up with an incomplete implementation of it (e.g., cells corrected but not the technology LEF), then it's the tools that need to be fixed (or possibly the tool setup). Which tools specifically are unable to cope with the nwell/pwell masterslice layers?