Hi, when i convert the extracted layout to spice(netlist) format in magic and open the spice file, my layout i see the scale option 5000u. What does it means? if i take the PMOS transistor, the size is w= 230 and l=30. what will be the total width of Pmos ? is that total width is 230 x 5000u = 1150000u? how can we make the scale factor is 1 in order to get w=230nm? Also l=30 , what does it means in nm length??? The length and width parameters are not cleared if i use magic with Skywater 130nm pdk. Q1.png