Join Slack
Powered by
and if so, what's the expected advantage here? At ...
# sky130
t
Trevor Clarke
11/16/2020, 7:34 PM
and if so, what's the expected advantage here? At least in the discreet world, you'd usually do this for increased current handling in power stages...are there other advantages in VLSI? Maybe decreased gate resistance?
Open in Slack
Previous
Next