@User: enable_h is basically a "vddio power good" signal, and enable_vdda_h is basically a "vdda power good signal". There are references in the I/O documentation to a power-on-reset cell that we don't have. I am creating a power-on-reset circuit for Caravel that has a slow ramp (15ms) followed by a schmitt trigger buffer for hysteresis, and should provide a good signal for these connections (see the caravel repository, develop branch, spice/verilog/layout for cell "simple_por"). You can also use the output from the "xres" pads, which is a glitch-free reset signal. If you leave the pad floating, then the output should act like a power-on-reset signal.