I am using the power on reset circuit from caravel repository that instantiates "sky130_fd_sc_hvl__schmittbuf_1.v" and "sky130_fd_sc_hvl__lsbufhv2lv_1.v" while instiantiating it from the pdk it shows error in the pdk verilog netlist itself `default_nettype none `timescale 1 ns / 1 ps `include "sky130_fd_sc_hvl__schmittbuf_1.v" `include "sky130_fd_sc_hvl__lsbufhv2lv_1.v" module simple_por( inout vdd3v3, inout vdd1v8, inout vss, output porb_h, output porb_l, output por_l); wire mid, porb_h; reg inode; // This is a behavioral model! Actual circuit is a resitor dumping // current (slowly) from vdd3v3 onto a capacitor, and this fed into // two schmitt triggers for strong hysteresis/glitch tolerance. initial begin inode <= 1'b0; end // Emulate current source on capacitor as a 500ns delay either up or // down. always @(posedge vdd3v3) begin #500 inode <= 1'b1; end always @(negedge vdd3v3) begin #500 inode <= 1'b0; end // Instantiate two shmitt trigger buffers in series sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 ( `ifdef USE_POWER_PINS .VPWR(vdd3v3), .VGND(vss), .VPB(vdd3v3), .VNB(vss), `endif .A(inode), .X(mid) ); sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 ( `ifdef USE_POWER_PINS .VPWR(vdd3v3), .VGND(vss), .VPB(vdd3v3), .VNB(vss), `endif .A(mid), .X(porb_h) ); sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level ( `ifdef USE_POWER_PINS .VPWR(vdd3v3), .VPB(vdd3v3), .LVPWR(vdd1v8), .VNB(vss), .VGND(vss), `endif .A(porb_h), .X(porb_l) ); // since this is behavioral anyway, but this should be // replaced by a proper inverter assign por_l = ~porb_l; endmodule `default_nettype wire and the below one is sky130_fd_sc_hvl__schmittbuf_1 /** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HVL__SCHMITTBUF_1_V `define SKY130_FD_SC_HVL__SCHMITTBUF_1_V /** * schmittbuf: Schmitt Trigger Buffer. * * Verilog wrapper for schmittbuf with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hvl__schmittbuf.v" `ifdef USE_POWER_PINS /*******************/ `celldefine module sky130_fd_sc_hvl__schmittbuf_1 ( X , A , VPWR, VGND, VPB , VNB ); output X ; input A ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hvl__schmittbuf cell ( .X(X), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*******************/ `else // If not USE_POWER_PINS /*******************/ `celldefine module sky130_fd_sc_hvl__schmittbuf_1 ( X , A , VPWR, VGND, VPB , VNB ); output X ; input A ; input VPWR; input VGND; input VPB ; input VNB ; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hvl__schmittbuf cell ( .X(X), .A(A) ); endmodule `endcelldefine /*******************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_HVL__SCHMITTBUF_1_V