I'm wondering if anyone can point me to some resources on diagnosing LVS issues -- haven't been able to find anything via Google yet. I'm getting a large number of net-mismatch issues at the top (user_project_wrapper) level. My understanding is that I should be looking at the spice netlist and the powered verilog netlist.

Circuit 1 contains 753 devices, Circuit 2 contains 753 devices.
Circuit 1 contains 3475 nets,    Circuit 2 contains 2574 nets. *** MISMATCH ***

Result: Netlists do not match.
Logging to file "/mkdv_rundir/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.lef.log" disabled
LVS Done.
LVS reports:
    net count difference = 901
    device count difference = 0
    unmatched nets = 228
    unmatched devices = 18
    unmatched pins = 0
    property failures = 0

Total errors = 1147

In looking at the report, it seems that the macros are connected in the Verilog with a different-named (short-named) net.

Net: u_sys_ic/dma_dat_r[30]                |(no matching net)
  clusterv_sys_ic/dma_dat_r[30] = 1        |
  clusterv_periph_subsys/dma_dat_r[30] = 1 |

Spice:

+ u_sys_ic/dma_dat_r[2] u_sys_ic/dma_dat_r[30] u_sys_ic/dma_dat_r[31]

Verilog:

wire \dma2ic_dat_r[2] ;
  wire \dma2ic_dat_r[30] ;
  wire \dma2ic_dat_r[31] ;
// ...
  clusterv_periph_subsys u_periph_subsys (
// ...
    .dma_dat_r({ \dma2ic_dat_r[31] , \dma2ic_dat_r[30] , \dma2ic_dat_r[29] , \dma2ic_dat_r[28]
// ...
  clusterv_sys_ic u_sys_ic (
// ...
    .dma_dat_r({ \dma2ic_dat_r[31] , \dma2ic_dat_r[30] , \dma2ic_dat_r[29] ,

Note that the pin on both modules are connected in the Verilog, just using a different net name. Any ideas on what could be going wrong here, or resources I can use to learn more would be much appreciated!