Hi There   If you have participated in "Verilog RTL design and synthesis 5-day workshop using Sky130", you will receive workshop login details on 22nd June. But if you haven't, this is a gentle reminder that registration closes in 3 days on 21st June, 11:59pm IST. So you might want to hurry up:   This workshop has been recognized as the best one for freshers, if you are looking for an early career in VLSI and Semiconductors. All labs start from very basic and connects you to industry   Timings - This is the only VLSI workshop, which happens on cloud. You can login at your convenient time, complete lectures/labs for that day and logout. We have a slack channel for 24/7 LIVE interactions with experts. So you can work from whichever time-zone you are in. Workshop starts on 23rd June - 00:00hrs IST and ends on 27th June 11:59PM IST Registration link: https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/   Re-sharing the curriculum again here:   Workshop Day wise Content : Day 1 - Introduction to Verilog RTL design and Synthesis • Introduction to open-source simulator iverilog • Labs using iverilog and gtkwave • Introduction to Yosys and Logic synthesis • Labs using Yosys and Sky130 PDKs Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles • Introduction to timing .libs • Hierarchical vs Flat Synthesis • Various Flop Coding Styles and optimization Day 3 - Combinational and sequential optmizations • Introduction to optimizations • Combinational logic optimizations • Sequential logic optimizations • Sequential optimzations for unused outputs Day 4 - GLS, blocking vs non-blocking and Synthesis-Simulation mismatch • GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements • Labs on GLS and Synthesis-Simulation Mismatch • Labs on synth-sim mismatch for blocking statement Day 5 - Optimization in synthesis • If Case constructs • Labs on "Incomplete If Case" • Labs on "Incomplete overlapping Case" • for loop and for generate • Labs on "for loop" and "for generate" All the best and happy learning.