@User, @User: yosys does not use cells like FA and HA by default. However, it has methods by which any of its intermediate form structures can be given a specific implementation and mapping. There are a number of such mappings in Openlane; see, e.g.,

open_pdks/sky130/openlane/sky130_fd_sc_hd/fa_map.v

. It is only necessary to read these verilog files into yosys before synthesis.