Hi all, I am new to Slack in general and also to this project. I used to design cellphone radio ICs but have moved to a place where there is not much chip design, so I am excited by the possibility of doing some again as a hobby (if only I had time!). From my experiences of RF IC design I would suggest not putting much work into the inductor models in the PDK, as I think chip designers will generally not use them. In my job we certainly never used the foundry-provided models as (a) we didn't trust them, and (b) the structures provided were not well optimised. Inductors consume extremely expensive amounts of die area and are critical to performance of some RF circuits, so it is worth optimising them, and usually the layout is closely interdependent on the circuit in which they will be used. For example square layouts give worse Q than octagonal, so usually octagonal inductors are wanted, and many circuit topologies require centre-tapped differential inductors, but the foundry models usually don't provide these. Also any traces connecting the inductor to a tuning capacitor bank will have inductance and mutual inductance with the inductor, so the inductor design really should be treated as part of the circuit design task. We used expensive commercial field solvers but with careful application and perseverence, splitting the inductor up into parts of its turns for simulation, FastCap and FastHenry can be made to do the job well. Beyond just providing a proof of concept inductor cell, I would suggest just making sure that the marker layers work well enough that a designer can import their own inductor layout and provide their own spice subcircuit as a model for it, and make it easy to pass LVS/DRC without defeating checks of the rest of the circuit, with the onus being on the designer to make sure that the inductor layout itself is ok and that the model matches the geometry. Preventing unwanted coupling between inductors and traces or other inductors is its own topic, and leads to all sorts of shields being incorporated into the inductor structures to reduce capacitive coupling, with slots and gaps in the shields to prevent shorted turns. Designers will likely want to keep a clear space around the inductor with a diameter about twice that of the inductor, to reduce magnetic coupling to traces. Making that space pass metal density checks might be interesting, though sometimes it is OK to insert some fill patterns. Some guidance on when density checking can be waived without the project getting rejected might be useful.