@User Yes, that would be useful. In my job we did create a script that could generate a number of different patterns with configurable sizes, and spat that out as a CIF file (as I couldn't figure out GDSII) and also it spat out a FastHenry and FastCap geometry files. In FastHenry, each part of each turn was simulated as its own inductor (with all of the mutual inductances too), and in the FastCap model, each part of each turn was a separate conductor. Then it ran FastCap and FastHenry and merged all of the inductors, mutual inductors and capacitors into a spice subcircuit. This worked pretty well where the wavelength was much larger than chip dimensions. It might be hard to know what structures/features people want in advance though. At least if it is open source, people could add the structure that they need.