in the xschem standard distribution i have a <8k x...
# analog-design
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in the xschem standard distribution i have a 8k x16bit ROM that i have simulated with ngspice (14K mos transistors). The stimuli for ngspice is generated using utile, a stimuli processing language, another tool that comes with xschem: the read cycles to run the simulation with ngspcice are coded like this: ~ unit n voltage VCC slope 0.2 format hspice buswidth LDA 13 [ ] buswidth LDSALDEL 2 [ ] buswidth LDPRECHDEL 2 [ ] param tck 16 param tah 2.5 param tas 2.5 alias cycle add en oe set LDEN en set LDOE oe set LDA add s tas set LDCP 1 s tah set LDEN 0 set LDA 0000 s tck/2-tah set LDCP 0 s tck/2-tas endalias beginfile stimuli_rom8k.cir set VCC 0 set LDCP 0 set LDA 0000 set LDEN 0 s tck-0.1 set VCC 1 s 100 s tck-tas ; add en oe ;===================== cycle 0000 1 1 cycle 0011 1 1 cycle 0022 1 1 cycle 0033 1 1 cycle 0044 1 1 cycle 0055 1 1 cycle 0066 1 1 cycle 0107 1 1 cycle 0077 1 1 cycle 0088 1 1 cycle 0099 1 1 cycle 00aa 1 1 cycle 00bb 1 1 cycle 00cc 1 1 cycle 00dd 1 1 cycle 00ee 1 1 cycle 0000 0 0 endfile ~ This stimuli is then translated to spice PWL voltage sources: ... ... VLDA[5] LDA[5] 0 PWL 0n 0 161.4n 0 161.6n VCC 166.4n VCC 166.6n 0 177.4n +0 177.6n VCC 182.4n VCC 182.6n 0 225.4n 0 225.6n VCC 230.4n VCC 230.6n 0 +257.4n 0 257.6n VCC 262.4n VCC 262.6n 0 305.4n 0 305.6n VCC 310.4n VCC 310.6n +0 321.4n 0 321.6n VCC 326.4n VCC 326.6n 0 369.4n 0 369.6n VCC 374.4n VCC +374.6n 0 VLDA[6] LDA[6] 0 PWL 0n 0 193.4n 0 193.6n VCC 198.4n VCC 198.6n 0 209.4n +0 209.6n VCC 214.4n VCC 214.6n 0 225.4n 0 225.6n VCC 230.4n VCC 230.6n 0 +257.4n 0 257.6n VCC 262.4n VCC 262.6n 0 337.4n 0 337.6n VCC 342.4n VCC 342.6n +0 353.4n 0 353.6n VCC 358.4n VCC 358.6n 0 369.4n 0 369.6n VCC 374.4n VCC +374.6n 0 ... ...