<@U01819B63HP> thanks for the update. Since `inver...
# analog-design
i
@User thanks for the update. Since
inverter.spice
was generated with openlane (with an updated version of skywater-pdk to connect to missing ports for fill/dcap cells, see https://github.com/efabless/openlane/issues/84) I would assume there is another bug in the PDK, perhaps already fixed an an even newer version. But now it's too late in the evening for me to debug and report it further. It will wait for tomorrow.