In some designs reverse body bias is used to reduce leakage power in stand-by modes. This can be achieved either by supplying <0 / >VDD well voltages for N/P transistors (for N only if in insulated pwell) or -easier- by disconnecting source terminals. Rasing the source (for N, reverse for P) will reduce Vgs and also increase Vth, so leakage is reduced. This 'sleep' mode is thus achieved by floating the supply rail of entire parts of the logic, while keeping body connections. This sleep mode can also be engineered to preserve the state of the circuit, by disconnecting alternate N-source / P-source in logic circuits, so internal states of all nodes is not lost. The drawback is of course the recovery time to reset supply rails when going beck to active mode. For increasing speed in some cases forward body bias is used (some 100mVolts, with lot of care, as body current injection must be kept low, the body-source diode must never be turned on), this is especially useful for cryogenic equipments, since thresholds / Vbe will be higher. This paper shows some numbers on a cmos process...