Does anyone have any examples of using netgen for doing LVS for mixed signal (digital cells and analog)? I am having problems getting the digital cells to be flattened in the spice files. Looking through the pdk provided sky130A_setup.tcl script for netgen there seems to be specific code to handle the digital cells. But that code seems to actually be preventing the logic cells from being flattened to the transistor level. So if I flatten my layout in magic they do not match.